In the so-called RDS system (Radio Data System), radio stations broadcast RDS information transmitting station identification, alternative frequencies of the radio station, program types etc. More details in this respect are described in the publication "Specifications of the Radio Data System RDS for VHF/FM Sound Broadcasting", Tech. 3244-E, Technical Centre of the European Broadcasting Union, Brussels, March 1984.
RDS information is transmitted in the form of a signal that is biphase-modulated with a binary bit sequence. With such a biphase-modulated signal, each RDS bit may be divided into two half bits. A phase reversal takes place at the half bit transition between two half bits belonging to one RDS bit. At the bit change between two adjacent RDS bits representing different logic values "0" and "1", a sudden phase change of 180.degree. occurs in the carrier oscillation of the transmitted RDS signal. As a carrier for the RDS signal, a carrier frequency of 57 kHz is employed. This carrier is suppressed on the transmitter side before the radio signal is broadcast. The carrier frequency thus has to be recovered on the receiver side, which is effected with the aid of a quartz oscillator on the receiver side. The RDS information is broadcast on the transmitter side with a bit rate of 1187.5 Hz. In order to be able to demodulate the received RDS signal on the receiver side, a bit rate clock signal with the same rectangular frequency has to be generated on the receiver side. This is effected by dividing the frequency of the 57 kHz oscillator signal produced on the receiver side by the value 48.
In order to allow proper decoding of the digital RDS signal demodulated on the receiver side, the bit rate clock signal generated on the receiver side must be in phase synchronism with the demodulated digital RDS signal. This is effected conventionally with a so-called "Costas loop" providing edge coincidence of the digital RDS signal demodulated on the receiver side and the bit rate clock signal generated on the receiver side, irrespective of whether RDS signal edges and bit rate clock signal edges having the same direction or opposite directions with respect to time are brought into coincidence.
An ordinary PLL uses for each bit period a sample value of a signal in order to synchronize it in terms of phase with another signal. In case of the Costas loop, a sample pair of two samples shifted by 90.degree. from each other is used for each bit period. In the Costas loop, for example, at the time of the rising edge, a first sample value is taken of the digital RDS signal demodulated on the receiver side, and at a later time corresponding to a phase angle of 90.degree. a second sample value of the digital RDS signal is taken. When the two samples belonging to a respective sample pair have different digital values of the RDS signal, it is assumed that the bit rate clock signal is in phase lead with respect to the digital RDS signal. When the two samples of the RDS signal belonging to a sample pair, in contrast thereto, have the same digital values, it is assumed that the bit rate clock signal generated on the receiver side is phase lagging with respect to the RDS signal. This difference in the sample values of the respectively associated sample pairs is used for establishing phase synchronism between the edges of RDS signal and bit rate clock signal. When the sample values of the respectively associated sample pairs have different digital values, the bit rate clock signal is shifted by a positive phase angle of predetermined phase angle amount. If however the two samples of the sample pairs have the same digital values, the bit rate clock signal is shifted by a negative phase angle of the predetermined phase angle amount.
The problem recognized by applicants is that these assumptions do not always hold true. For example, with this known phase synchronization method, in case the bit rate clock signal produced on the receiver side is in phase lead with respect to the demodulated digital RDS signal, sample pairs having the same digital values are obtained when two adjacent RDS bits meet each other which represent different logic values "0" and "1", respectively. At these locations, the phase synchronization circuit erroneously assumes that the bit rate clock signal is phase lagging with respect to the RDS signal. Thus, in case of such logic value changes between adjacent RDS bits, an erroneous regulating operation takes place in the phase synchronization circuit.